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authorZiyuan Xu <xzy.xu@rock-chips.com>2016-09-17 13:20:11 (GMT)
committerchrome-bot <chrome-bot@chromium.org>2016-12-10 05:46:39 (GMT)
commit0091f06cd4a27f16d1ff734730089dade4e23a28 (patch)
tree28326515d7c468409862d2e834942c1f603a3138 /src
parent94804e200a84c1232888cae49e604d2d0e81277a (diff)
downloaddepthcharge-0091f06cd4a27f16d1ff734730089dade4e23a28.tar.gz
depthcharge-0091f06cd4a27f16d1ff734730089dade4e23a28.tar.xz
mmc: select appropriate timing after speed mode switch
Select timing parameters for host once speed mode switch is completed. BUG=chrome-os-partner:54377 BRANCH=master TEST=build and boot on kevin Change-Id: Icb10482318beb4d85eab94f40561847497c95947 Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Reviewed-on: https://chromium-review.googlesource.com/386519 Commit-Ready: Julius Werner <jwerner@chromium.org> Tested-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/drivers/storage/mmc.c15
-rw-r--r--src/drivers/storage/mmc.h13
2 files changed, 27 insertions, 1 deletions
diff --git a/src/drivers/storage/mmc.c b/src/drivers/storage/mmc.c
index 3e3cc97..6a55f37 100644
--- a/src/drivers/storage/mmc.c
+++ b/src/drivers/storage/mmc.c
@@ -492,6 +492,12 @@ static void mmc_set_bus_width(MmcCtrlr *ctrlr, uint32_t width)
ctrlr->set_ios(ctrlr);
}
+static void mmc_set_timing(MmcCtrlr *ctrlr, uint32_t timing)
+{
+ ctrlr->timing = timing;
+ ctrlr->set_ios(ctrlr);
+}
+
static int mmc_change_freq(MmcMedia *media)
{
char cardtype;
@@ -526,12 +532,17 @@ static int mmc_change_freq(MmcMedia *media)
if (err)
return err;
+ mmc_set_timing(media->ctrlr, MMC_TIMING_MMC_HS200);
+
/* Adjust Host Bus Wisth to 8-bit */
mmc_set_bus_width(media->ctrlr, 8);
media->caps |= EXT_CSD_BUS_WIDTH_8;
} else {
err = mmc_switch(media, EXT_CSD_CMD_SET_NORMAL,
EXT_CSD_HS_TIMING, 1);
+
+ if (!err)
+ mmc_set_timing(media->ctrlr, MMC_TIMING_MMC_HS);
}
if (err)
@@ -675,8 +686,10 @@ static int sd_change_freq(MmcMedia *media)
if (err)
return err;
- if ((ntohl(switch_status[4]) & 0x0f000000) == 0x01000000)
+ if ((ntohl(switch_status[4]) & 0x0f000000) == 0x01000000) {
media->caps |= MMC_MODE_HS;
+ mmc_set_timing(media->ctrlr, MMC_TIMING_SD_HS);
+ }
return 0;
}
diff --git a/src/drivers/storage/mmc.h b/src/drivers/storage/mmc.h
index 3827ef2..c30c5ee 100644
--- a/src/drivers/storage/mmc.h
+++ b/src/drivers/storage/mmc.h
@@ -245,6 +245,19 @@ typedef struct MmcCtrlr {
uint32_t bus_hz;
uint32_t caps;
uint32_t b_max;
+ uint32_t timing;
+
+#define MMC_TIMING_LEGACY 0
+#define MMC_TIMING_MMC_HS 1
+#define MMC_TIMING_SD_HS 2
+#define MMC_TIMING_UHS_SDR12 3
+#define MMC_TIMING_UHS_SDR25 4
+#define MMC_TIMING_UHS_SDR50 5
+#define MMC_TIMING_UHS_SDR104 6
+#define MMC_TIMING_UHS_DDR50 7
+#define MMC_TIMING_MMC_DDR52 8
+#define MMC_TIMING_MMC_HS200 9
+#define MMC_TIMING_MMC_HS400 10
/*
* Some eMMC devices do not support iterative OCR setting, they need