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authorNaveen Krishna Chatradhi <naveenkrishna.ch@intel.com>2015-12-18 10:53:12 (GMT)
committerchrome-bot <chrome-bot@chromium.org>2016-02-04 09:44:53 (GMT)
commitac2b89a9590b92aae48c4232bcd1c4d296ac4c10 (patch)
treea5edc8cf77e6d8d34c812693afd23192f4267afe
parent065ba14bc56c9044247fef6337d8f9e9a3055820 (diff)
downloaddepthcharge-stabilize-smaug-7897.B.tar.gz
depthcharge-stabilize-smaug-7897.B.tar.xz
Kunimitsu/Lars: Workaround for silego unable to see EC resetstabilize-smaug-7897.Bstabilize-7907.B
On skylake boards the silego chip is unable to see EC resets and clear the latch on EC_IN_RW state. This means that FAFT is unable to switch to developer mode because VbExTrustEC() will always fail. This only matters for FAFT because entering recovery mode with the keyboard still works properly and this VbExTrustEC() callback is only ever used in the developer mode transition screen. As such, use the existing FAFT override GBB flag that is used for similar workarounds in the firmware to enable FAFT testing. This is a bit messy, using an overridden flag to check at runtime, because GBB flags are not available in the board_setup() function as they have not been read yet and due to the structure of RO/RW depthcharge it is not convenient to change that behavior. This is a port for Kunimitsu and lars boards following CL for https://chromium-review.googlesource.com/#/c/319245/ BUG=chrome-os-partner:47648 BRANCH=none TEST=manual testing (in additon to FAFT) 1) set GBB flag 0x300 2) enter recovery mode with: dut-control power_state:rec 3) press Ctrl+D on keyboard to transition to developer mode 4) also verify that when the GBB flag is not set that if the EC is in RW and steps 2-3 are executed that it does not allow entry into developer mode 5) also verify that keyboard controlled recovery mode does clear the EC_IN_RW flag properly and does not need GBB flag to be set. Change-Id: Icd120cbff4d19b51f193c5ed9c40ec3098820f5e Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com> Reviewed-on: https://chromium-review.googlesource.com/319208 Commit-Ready: Divya Jyothi <divya.jyothi@intel.com> Tested-by: Divagar Mohandass <divagar.mohandass@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
-rwxr-xr-xsrc/board/kunimitsu/board.c32
-rwxr-xr-xsrc/board/lars/board.c32
2 files changed, 64 insertions, 0 deletions
diff --git a/src/board/kunimitsu/board.c b/src/board/kunimitsu/board.c
index d333fea..d3d5773 100755
--- a/src/board/kunimitsu/board.c
+++ b/src/board/kunimitsu/board.c
@@ -21,6 +21,7 @@
* MA 02111-1307 USA
*/
+#include <gbb_header.h>
#include <pci.h>
#include <pci/pci.h>
#include <libpayload.h>
@@ -46,6 +47,7 @@
#include "drivers/tpm/lpc.h"
#include "drivers/tpm/tpm.h"
#include "vboot/util/flag.h"
+#include "vboot/util/commonparams.h"
#include "drivers/bus/usb/usb.h"
/*
@@ -58,9 +60,39 @@
#define EMMC_CLOCK_MAX 200000000
#define SD_CLOCK_MAX 52000000
+/*
+ * Workaround for issue where silego is unable to see EC reset to clear the
+ * EC_IN_RW state when attempting to enter recovery via servo. This allows FAFT
+ * to transition the system to developer mode.
+ */
+static int ec_in_rw_workaround_get_value(GpioOps *me)
+{
+ GoogleBinaryBlockHeader *gbb = cparams.gbb_data;
+
+ if (gbb->flags & GBB_FLAG_FAFT_KEY_OVERIDE) {
+ /* Override is enabled, return 0 for FAFT. */
+ printf("FAFT override enabled, returning 0 for ECINRW flag\n");
+ return 0;
+ }
+
+ /* Override is not enabled, lookup the real GPIO state. */
+ GpioOps *ecinrw = sysinfo_lookup_gpio("EC in RW", 1,
+ new_skylake_gpio_input_from_coreboot);
+ return ecinrw->get(ecinrw);
+}
+
+GpioOps *ec_in_rw_workaround_gpio(void)
+{
+ GpioOps *ops = xzalloc(sizeof(*ops));
+
+ ops->get = &ec_in_rw_workaround_get_value;
+ return ops;
+}
+
static int board_setup(void)
{
sysinfo_install_flags(new_skylake_gpio_input_from_coreboot);
+ flag_replace(FLAG_ECINRW, ec_in_rw_workaround_gpio());
/* MEC1322 Chrome EC */
CrosEcLpcBus *cros_ec_lpc_bus =
diff --git a/src/board/lars/board.c b/src/board/lars/board.c
index 9ac5e2e..f815dc0 100755
--- a/src/board/lars/board.c
+++ b/src/board/lars/board.c
@@ -21,6 +21,7 @@
* MA 02111-1307 USA
*/
+#include <gbb_header.h>
#include <pci.h>
#include <pci/pci.h>
#include <libpayload.h>
@@ -42,6 +43,7 @@
#include "drivers/tpm/lpc.h"
#include "drivers/tpm/tpm.h"
#include "vboot/util/flag.h"
+#include "vboot/util/commonparams.h"
#include "drivers/bus/usb/usb.h"
/*
@@ -53,9 +55,39 @@
#define EMMC_SD_CLOCK_MIN 400000
#define EMMC_CLOCK_MAX 200000000
+/*
+ * Workaround for issue where silego is unable to see EC reset to clear the
+ * EC_IN_RW state when attempting to enter recovery via servo. This allows FAFT
+ * to transition the system to developer mode.
+ */
+static int ec_in_rw_workaround_get_value(GpioOps *me)
+{
+ GoogleBinaryBlockHeader *gbb = cparams.gbb_data;
+
+ if (gbb->flags & GBB_FLAG_FAFT_KEY_OVERIDE) {
+ /* Override is enabled, return 0 for FAFT. */
+ printf("FAFT override enabled, returning 0 for ECINRW flag\n");
+ return 0;
+ }
+
+ /* Override is not enabled, lookup the real GPIO state. */
+ GpioOps *ecinrw = sysinfo_lookup_gpio("EC in RW", 1,
+ new_skylake_gpio_input_from_coreboot);
+ return ecinrw->get(ecinrw);
+}
+
+GpioOps *ec_in_rw_workaround_gpio(void)
+{
+ GpioOps *ops = xzalloc(sizeof(*ops));
+
+ ops->get = &ec_in_rw_workaround_get_value;
+ return ops;
+}
+
static int board_setup(void)
{
sysinfo_install_flags(new_skylake_gpio_input_from_coreboot);
+ flag_replace(FLAG_ECINRW, ec_in_rw_workaround_gpio());
/* MEC1322 Chrome EC */
CrosEcLpcBus *cros_ec_lpc_bus =