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authorBora Guvendik <bora.guvendik@intel.com>2016-08-05 23:13:13 (GMT)
committerchrome-bot <chrome-bot@chromium.org>2016-08-09 03:19:52 (GMT)
commit51ad169449815ad9415f588d013541ca263ffff9 (patch)
tree46915f1350f08678ba901b971b836125c9d9228c
parentb9c9437c05204bf7cbe91d686b2284146582b76e (diff)
downloaddepthcharge-stabilize-8688.B.tar.gz
depthcharge-stabilize-8688.B.tar.xz
Amenia: Change flash image size to 16MBstabilize-8688.B
Update fmap.dts file for 16MB flash image size Change fmap.dts based on flash layout changes in chromeos.fmd Increase BIOS region size BUG=chrome-os-partner:51844 TEST=Boot to chrome Change-Id: I085f5eaaafe6c84954c9e86df631204b4e5dc86f Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://chromium-review.googlesource.com/366831 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
-rw-r--r--board/amenia/defconfig3
-rw-r--r--board/amenia/fmap.dts182
-rw-r--r--src/board/amenia/board.c8
3 files changed, 146 insertions, 47 deletions
diff --git a/board/amenia/defconfig b/board/amenia/defconfig
index 1503a86..a546606 100644
--- a/board/amenia/defconfig
+++ b/board/amenia/defconfig
@@ -5,7 +5,7 @@ CONFIG_ARCH_X86=y
CONFIG_BOARD="amenia"
# Image
-CONFIG_FMAP_OFFSET=0x00200000
+CONFIG_FMAP_OFFSET=0x00204000
# Vboot
CONFIG_EC_SOFTWARE_SYNC=y
@@ -28,4 +28,3 @@ CONFIG_DRIVER_SDHCI=y
CONFIG_DRIVER_STORAGE_MMC=y
CONFIG_DRIVER_STORAGE_SDHCI_PCI=y
CONFIG_DRIVER_TPM_LPC=y
-CONFIG_MOCK_TPM=y
diff --git a/board/amenia/fmap.dts b/board/amenia/fmap.dts
index 2084052..865f1c5 100644
--- a/board/amenia/fmap.dts
+++ b/board/amenia/fmap.dts
@@ -1,4 +1,11 @@
/dts-v1/;
+/*
+ * NOTE: this needs to align with src/mainboard/intel/amenia/chromeos.fmd
+ * in the coreboot repository. Any changes made there should be reflected
+ * in this file. There are parallel notions of fmap information. However,
+ * both are used in different parts of the system so the right answer now
+ * is to keep them in sync.
+ */
/ {
model = "Intel Amenia";
@@ -11,23 +18,13 @@
gbb-flag-force-dev-switch-on;
gbb-flag-force-dev-boot-usb;
gbb-flag-disable-fw-rollback-check;
+ gbb-flag-disable-ec-software-sync;
};
flash@ff800000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "chromeos,flashmap";
- reg = <0xff800000 0x00800000>;
-
- /*
- * Non-BIOS section of the Intel Firmware Descriptor image.
- * This section covers the all the parts that are not shown
- * to the CPU right below 4G.
- */
- si-all {
- label = "si-all";
- reg = <0x00000000 0x00200000>;
- type = "ifd";
- };
+ reg = <0xff800000 0x01000000>;
/*
* Firmware Descriptor section of the Intel Firmware Descriptor
@@ -36,10 +33,21 @@
si-desc {
label = "si-desc";
reg = <0x00000000 0x00001000>;
+ type = "ifd";
};
- bootblock {
- label = "bootblock";
- reg = <0x00076480 0x00008000>;
+ ro-ifwi {
+ label = "ifwi";
+ reg = <0x00001000 0x001ff000>;
+ read-only;
+ required;
+ type = "blob ifwi";
+ };
+ ro-vpd {
+ label = "ro-vpd";
+ reg = <0x00200000 0x00004000>;
+ read-only;
+ type = "wiped";
+ wipe-value = [ff];
};
ro-fmap {
label = "fmap";
@@ -50,56 +58,73 @@
* 256KB.
*/
- reg = <0x00200000 0x00000800>;
+ reg = <0x00204000 0x00000800>;
read-only;
type = "fmap";
ver-major = <1>;
- ver-minor = <1>;
+ ver-minor = <0>;
};
- ro-frid {
+ ro-firmware-id {
label = "ro-frid";
- reg = <0x00200800 0x00000040>;
+ reg = <0x00204800 0x00000040>;
read-only;
+ type = "blobstring fwid";
};
- ro-vpid {
- label = "ro-vpid";
- reg = <0x00201000 0x00004000>;
+ ro-frid-pad {
+ label ="ro-frid-pad";
+ reg = <0x00204840 0x000007c0>;
read-only;
+ type = "wiped";
+ wipe-value = [ff];
};
ro-boot {
label = "coreboot";
- reg = <0x00205000 0x0013d000>;
+ reg = <0x00205000 0x0017b000>;
read-only;
type = "blob coreboot";
required;
};
+ ro-gbb {
+ label = "gbb";
+ /* GBB offset must be aligned to 4K bytes */
+ reg = <0x00380000 0x00040000>;
+ read-only;
+ type = "blob gbb";
+ };
+ ro-unused-1 {
+ label ="ro-unused-1";
+ reg = <0x003c0000 0x00400000>;
+ read-only;
+ type = "wiped";
+ wipe-value = [ff];
+ };
ro-sig2 {
label = "sign_cse";
- reg = <0x00380000 0x0001000>;
+ reg = <0x007c0000 0x00010000>;
read-only;
required;
+ type = "blob sig2";
};
- ro-gbb {
- label = "gbb";
-
- /* GBB offset must be aligned to 4K bytes */
- reg = <0x00390000 0x00050000>;
+ ro-unused-2 {
+ label ="ro-unused-2";
+ reg = <0x007d0000 0x00030000>;
read-only;
- type = "blob gbb";
+ type = "wiped";
+ wipe-value = [ff];
};
/* ---- Section: Rewritable MRC cache 64KB ---- */
rw-mrc-cache {
label = "rw-mrc-cache";
/* Alignment: 4k (for updating) */
- reg = <0x00400000 0x00010000>;
+ reg = <0x00800000 0x00010000>;
type = "wiped";
wipe-value = [ff];
};
- /* ---- 8k of event log */
+ /* ---- 16k of event log ---- */
rw-elog {
label = "rw-elog";
/* Alignment: 4k (for updating) */
- reg = <0x00410000 0x00004000>;
+ reg = <0x00810000 0x00004000>;
type = "wiped";
wipe-value = [ff];
};
@@ -110,7 +135,7 @@
* Anything in this range may be updated in recovery.
*/
label = "rw-shared";
- reg = <0x00414000 0x00004000>;
+ reg = <0x00814000 0x00004000>;
};
shared-data {
label = "shared-data";
@@ -118,15 +143,35 @@
* Alignment: 4k (for random read/write).
* RW firmware can put calibration data here.
*/
- reg = <0x00414000 0x00002000>;
+ reg = <0x00814000 0x00002000>;
type = "wiped";
wipe-value = [00];
};
+ rw-vblock-dev {
+ label = "vblock-dev";
+ /*
+ * Alignment: 4k (for random read/write).
+ * Reserve space for an optional user-installed
+ * vblock to validate dev-mode kernels.
+ * See crosbug.com/p/11216.
+ */
+ reg = <0x00816000 0x00002000>;
+ type = "wiped";
+ wipe-value = [ff];
+ };
+ /* ---- Section: Rewritable VPD 8 KB ---- */
+ rw-vpd {
+ label = "rw-vpd";
+ /* Alignment: 4k (for updating) */
+ reg = <0x00818000 0x00002000>;
+ type = "wiped";
+ wipe-value = [ff];
+ };
/* ---- Section: Rewritable slot A ---- */
rw-a {
label = "rw-section-a";
/* Alignment: 4k (for updating) */
- reg = <0x00520000 0x000f0000>;
+ reg = <0x0081a000 0x0028f800>;
};
rw-a-vblock {
label = "vblock-a";
@@ -134,7 +179,7 @@
* Alignment: 4k (for updating) and must be in start of
* each RW_SECTION.
*/
- reg = <0x00520000 0x00010000>;
+ reg = <0x0081a000 0x00010000>;
type = "keyblock cbfs/rw/a-boot";
keyblock = "firmware.keyblock";
signprivate = "firmware_data_key.vbprivk";
@@ -145,14 +190,22 @@
rw-a-boot {
/* Alignment: no requirement (yet). */
label = "fw-main-a";
- reg = <0x00530000 0x000c0000>;
+ reg = <0x0082a000 0x0027f7c0>;
type = "blob cbfs/rw/a-boot";
};
+ rw-a-firmware-id {
+ /* Alignment: no requirement. */
+ label = "rw-fwid-a";
+ reg = <0x00aa97c0 0x00000040>;
+ read-only;
+ type = "blobstring fwid";
+ };
+
/* ---- Section: Rewritable slot B ---- */
rw-b {
label = "rw-section-b";
/* Alignment: 4k (for updating) */
- reg = <0x00610000 0x000f0000>;
+ reg = <0x00aa9800 0x0028f800>;
};
rw-b-vblock {
label = "vblock-b";
@@ -160,7 +213,7 @@
* Alignment: 4k (for updating) and must be in start of
* each RW_SECTION.
*/
- reg = <0x00610000 0x00010000>;
+ reg = <0x00aa9800 0x00010000>;
type = "keyblock cbfs/rw/b-boot";
keyblock = "firmware.keyblock";
signprivate = "firmware_data_key.vbprivk";
@@ -171,8 +224,55 @@
rw-b-boot {
label = "fw-main-b";
/* Alignment: no requirement (yet). */
- reg = <0x00620000 0x000c0000>;
+ reg = <0x00ab9800 0x0027f7c0>;
type = "blob cbfs/rw/b-boot";
};
+ rw-b-firmware-id {
+ label = "rw-fwid-b";
+ /* Alignment: no requirement. */
+ reg = <0x00d38fc0 0x00000040>;
+ read-only;
+ type = "blobstring fwid";
+ };
+
+ /* ---- Section: Storage to simulate NVRAM ---- */
+ rw-nvram {
+ label = "rw-nvram";
+ reg = <0x00d39000 0x00006000>;
+ type = "wiped";
+ wipe-value = [ff];
+ };
+
+ rw-legacy {
+ label = "rw-legacy";
+ reg = <0x00d3f000 0x00200000>;
+ type = "blob legacy";
+ read-only;
+ };
+
+ /* ---- Last 256KiB of BIOS is unusable. ---- */
+ bios-unusable {
+ label ="bios-unusable";
+ reg = <0x00f3f000 0x00040000>;
+ read-only;
+ type = "wiped";
+ wipe-value = [ff];
+ };
+
+ device-extension {
+ /* CSE RW data */
+ label = "device-extension";
+ reg = <0x00f7f000 0x00080000>;
+ type = "wiped";
+ wipe-value = [ff];
+ };
+
+ unused-hole {
+ label ="unused-hole";
+ reg = <0x00fff000 0x00001000>;
+ read-only;
+ type = "wiped";
+ wipe-value = [ff];
+ };
};
};
diff --git a/src/board/amenia/board.c b/src/board/amenia/board.c
index 5d06d97..71ef47f 100644
--- a/src/board/amenia/board.c
+++ b/src/board/amenia/board.c
@@ -33,12 +33,12 @@
#include "drivers/tpm/lpc.h"
#include "drivers/storage/sdhci.h"
-#define EMMC_SD_CLOCK_MIN 400000
-#define SD_CLOCK_MAX 52000000
-#define EMMC_CLOCK_MAX 200000000
+#define EMMC_SD_CLOCK_MIN 400000
+#define EMMC_CLOCK_MAX 200000000
+#define SD_CLOCK_MAX 52000000
/* Flash memory map size includes the 4K descriptor which is not accessible */
-#define FLASH_MEM_MAP_SIZE 0x77F000
+#define FLASH_MEM_MAP_SIZE 0xF7F000
#define FLASH_MEM_MAP_BASE ((uintptr_t)(0x100000000ULL - FLASH_MEM_MAP_SIZE))
static int board_setup(void)