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authorAaron Durbin <adurbin@chromium.org>2016-02-25 22:33:30 (GMT)
committerchrome-bot <chrome-bot@chromium.org>2016-02-26 13:56:14 (GMT)
commit124af94fa5599a0698e59bf3d73675eb52fc6879 (patch)
treece0eae6d1a1bc222c597359fc050a3fc7e429c3f
parent2f296befc4a3e5068569c5f8e7cc5212589fb4c0 (diff)
downloaddepthcharge-stabilize-7978.B.tar.gz
depthcharge-stabilize-7978.B.tar.xz
Legacy payloads may rely on the 8254 programmable interrupt timer. Therefore, always re-enable the 8254 timer by masking off the static clock gating enable bit. All existing skylake boards were adjusted to select DRIVERS_SOC_SKYLAKE and the PCR access was moved into drivers/soc/skylake. The soc driver subsystem infrastructure was added to more accurately reflect broader SoC support instead of jamming that information into an unrelated subsystem. BUG=chrome-os-partner:50214 BRANCH=glados TEST=Confirmed 8254 static clock gate bit cleared in legacy path. Change-Id: I161f331121f236cfdea3542f2d0649e2a81beda9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/329158 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
-rw-r--r--board/chell/defconfig2
-rw-r--r--board/glados/defconfig2
-rw-r--r--board/kunimitsu/defconfig2
-rw-r--r--board/lars/defconfig2
-rw-r--r--src/drivers/Kconfig1
-rw-r--r--src/drivers/Makefile.inc1
-rw-r--r--src/drivers/gpio/skylake.c24
-rw-r--r--src/drivers/soc/Kconfig17
-rw-r--r--src/drivers/soc/Makefile.inc14
-rw-r--r--src/drivers/soc/skylake.c50
-rw-r--r--src/drivers/soc/skylake.h44
11 files changed, 132 insertions, 27 deletions
diff --git a/board/chell/defconfig b/board/chell/defconfig
index ce3b1f5..e3dd9f5 100644
--- a/board/chell/defconfig
+++ b/board/chell/defconfig
@@ -26,11 +26,11 @@ CONFIG_DRIVER_EC_CROS=y
CONFIG_DRIVER_EC_CROS_LPC=y
CONFIG_DRIVER_EC_CROS_PASSTHRU=y
CONFIG_DRIVER_FLASH_MEMMAPPED=y
-CONFIG_DRIVER_GPIO_SKYLAKE=y
CONFIG_DRIVER_INPUT_PS2=y
CONFIG_DRIVER_INPUT_USB=y
CONFIG_DRIVER_POWER_PCH=y
CONFIG_DRIVER_SDHCI=y
+CONFIG_DRIVER_SOC_SKYLAKE=y
CONFIG_DRIVER_SOUND_GPIO_PDM=y
CONFIG_DRIVER_SOUND_ROUTE=y
CONFIG_DRIVER_SOUND_SSM4567=y
diff --git a/board/glados/defconfig b/board/glados/defconfig
index 44a43b7..9277006 100644
--- a/board/glados/defconfig
+++ b/board/glados/defconfig
@@ -25,11 +25,11 @@ CONFIG_DRIVER_EC_CROS=y
CONFIG_DRIVER_EC_CROS_LPC=y
CONFIG_DRIVER_EC_CROS_PASSTHRU=y
CONFIG_DRIVER_FLASH_MEMMAPPED=y
-CONFIG_DRIVER_GPIO_SKYLAKE=y
CONFIG_DRIVER_INPUT_PS2=y
CONFIG_DRIVER_INPUT_USB=y
CONFIG_DRIVER_POWER_PCH=y
CONFIG_DRIVER_SDHCI=y
+CONFIG_DRIVER_SOC_SKYLAKE=y
CONFIG_DRIVER_SOUND_GPIO_PDM=y
CONFIG_DRIVER_SOUND_ROUTE=y
CONFIG_DRIVER_SOUND_SSM4567=y
diff --git a/board/kunimitsu/defconfig b/board/kunimitsu/defconfig
index ffdb417..c842267 100644
--- a/board/kunimitsu/defconfig
+++ b/board/kunimitsu/defconfig
@@ -24,11 +24,11 @@ CONFIG_DRIVER_EC_CROS=y
CONFIG_DRIVER_EC_CROS_LPC=y
CONFIG_DRIVER_EC_CROS_PASSTHRU=y
CONFIG_DRIVER_FLASH_MEMMAPPED=y
-CONFIG_DRIVER_GPIO_SKYLAKE=y
CONFIG_DRIVER_INPUT_PS2=y
CONFIG_DRIVER_INPUT_USB=y
CONFIG_DRIVER_POWER_PCH=y
CONFIG_DRIVER_SDHCI=y
+CONFIG_DRIVER_SOC_SKYLAKE=y
CONFIG_DRIVER_SOUND_GPIO_I2S=y
CONFIG_DRIVER_SOUND_GPIO_PDM=y
CONFIG_DRIVER_SOUND_MAX98357A=y
diff --git a/board/lars/defconfig b/board/lars/defconfig
index fbe4c2a..415f7d6 100644
--- a/board/lars/defconfig
+++ b/board/lars/defconfig
@@ -22,11 +22,11 @@ CONFIG_DRIVER_EC_CROS=y
CONFIG_DRIVER_EC_CROS_LPC=y
CONFIG_DRIVER_EC_CROS_PASSTHRU=y
CONFIG_DRIVER_FLASH_MEMMAPPED=y
-CONFIG_DRIVER_GPIO_SKYLAKE=y
CONFIG_DRIVER_INPUT_PS2=y
CONFIG_DRIVER_INPUT_USB=y
CONFIG_DRIVER_POWER_PCH=y
CONFIG_DRIVER_SDHCI=y
+CONFIG_DRIVER_SOC_SKYLAKE=y
CONFIG_DRIVER_STORAGE_MMC=y
CONFIG_DRIVER_STORAGE_SDHCI_PCI=y
CONFIG_DRIVER_TPM_LPC=y
diff --git a/src/drivers/Kconfig b/src/drivers/Kconfig
index 3d9e33e..67c3db9 100644
--- a/src/drivers/Kconfig
+++ b/src/drivers/Kconfig
@@ -22,6 +22,7 @@ source src/drivers/gpio/Kconfig
source src/drivers/input/Kconfig
source src/drivers/net/Kconfig
source src/drivers/power/Kconfig
+source src/drivers/soc/Kconfig
source src/drivers/sound/Kconfig
source src/drivers/storage/Kconfig
source src/drivers/tpm/Kconfig
diff --git a/src/drivers/Makefile.inc b/src/drivers/Makefile.inc
index be429c9..0f68934 100644
--- a/src/drivers/Makefile.inc
+++ b/src/drivers/Makefile.inc
@@ -23,6 +23,7 @@ subdirs-y += gpio
subdirs-y += input
subdirs-y += net
subdirs-y += power
+subdirs-y += soc
subdirs-y += sound
subdirs-y += storage
subdirs-y += tpm
diff --git a/src/drivers/gpio/skylake.c b/src/drivers/gpio/skylake.c
index 5937451..f3ed85e 100644
--- a/src/drivers/gpio/skylake.c
+++ b/src/drivers/gpio/skylake.c
@@ -24,29 +24,7 @@
#include "base/container_of.h"
#include "drivers/gpio/gpio.h"
#include "drivers/gpio/skylake.h"
-
-/* Skylake PCR access to GPIO registers. */
-#define PCH_PCR_BASE_ADDRESS 0xfd000000
-
-/* Port Id lives in bits 23:16 and register offset lives in 15:0 of address. */
-#define PCH_PCR_PORTID_SHIFT 16
-
-/* PCR PIDs for the GPIO communities. */
-#define PCH_PCR_PID_GPIOCOM3 0xAC
-#define PCH_PCR_PID_GPIOCOM2 0xAD
-#define PCH_PCR_PID_GPIOCOM1 0xAE
-#define PCH_PCR_PID_GPIOCOM0 0xAF
-
-static uint8_t *pcr_port_regs(u8 pid)
-{
- uintptr_t reg_addr;
-
- /* Create an address based off of port id and offset. */
- reg_addr = PCH_PCR_BASE_ADDRESS;
- reg_addr += ((uintptr_t)pid) << PCH_PCR_PORTID_SHIFT;
-
- return (uint8_t *)reg_addr;
-}
+#include "drivers/soc/skylake.h"
/* There are 4 communities with 8 GPIO groups (GPP_[A:G] and GPD) */
struct gpio_community {
diff --git a/src/drivers/soc/Kconfig b/src/drivers/soc/Kconfig
new file mode 100644
index 0000000..e65d83a
--- /dev/null
+++ b/src/drivers/soc/Kconfig
@@ -0,0 +1,17 @@
+##
+## Copyright 2016 Google Inc. All rights reserved.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+config DRIVER_SOC_SKYLAKE
+ bool "Skylake SoC driver"
+ default n
+ select DRIVER_GPIO_SKYLAKE
diff --git a/src/drivers/soc/Makefile.inc b/src/drivers/soc/Makefile.inc
new file mode 100644
index 0000000..08bbaf3
--- /dev/null
+++ b/src/drivers/soc/Makefile.inc
@@ -0,0 +1,14 @@
+##
+## Copyright 2016 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+depthcharge-$(CONFIG_DRIVER_SOC_SKYLAKE) += skylake.c
diff --git a/src/drivers/soc/skylake.c b/src/drivers/soc/skylake.c
new file mode 100644
index 0000000..4e26ee9
--- /dev/null
+++ b/src/drivers/soc/skylake.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <libpayload.h>
+#include <stdint.h>
+
+#include "base/cleanup_funcs.h"
+#include "base/init_funcs.h"
+#include "drivers/soc/skylake.h"
+
+static int pit_8254_enable(struct CleanupFunc *cleanup, CleanupType type)
+{
+ /* Unconditionally enable the 8254 in the Legacy path. */
+ const uint32_t cge8254_mask_off = ~(1 << 2);
+ const int itssprc_offset = 0x3300;
+ void *itssprc = pcr_port_regs(PCH_PCR_PID_ITSS) + itssprc_offset;
+ uint32_t reg = read32(itssprc);
+
+ reg &= cge8254_mask_off;
+ write32(itssprc, reg);
+
+ return 0;
+}
+
+static int pit_8254_cleanup_install(void)
+{
+ static CleanupFunc dev =
+ {
+ &pit_8254_enable,
+ CleanupOnLegacy,
+ NULL
+ };
+
+ list_insert_after(&dev.list_node, &cleanup_funcs);
+ return 0;
+}
+
+INIT_FUNC(pit_8254_cleanup_install);
+
diff --git a/src/drivers/soc/skylake.h b/src/drivers/soc/skylake.h
new file mode 100644
index 0000000..2f524c6
--- /dev/null
+++ b/src/drivers/soc/skylake.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2016 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __DRIVERS_SOC_SKYLAKE_H__
+#define __DRIVERS_SOC_SKYLAKE_H__
+
+#include <stdint.h>
+
+/* Skylake PCR access to GPIO registers. */
+#define PCH_PCR_BASE_ADDRESS 0xfd000000
+
+/* Port Id lives in bits 23:16 and register offset lives in 15:0 of address. */
+#define PCH_PCR_PORTID_SHIFT 16
+
+/* PCR PIDs. */
+#define PCH_PCR_PID_GPIOCOM3 0xAC
+#define PCH_PCR_PID_GPIOCOM2 0xAD
+#define PCH_PCR_PID_GPIOCOM1 0xAE
+#define PCH_PCR_PID_GPIOCOM0 0xAF
+#define PCH_PCR_PID_ITSS 0xC4
+
+static inline void *pcr_port_regs(u8 pid)
+{
+ uintptr_t reg_addr;
+
+ /* Create an address based off of port id and offset. */
+ reg_addr = PCH_PCR_BASE_ADDRESS;
+ reg_addr += ((uintptr_t)pid) << PCH_PCR_PORTID_SHIFT;
+
+ return (void *)reg_addr;
+}
+
+#endif /* __DRIVERS_SOC_SKYLAKE_H__ */