diff options
authorIonela Voinescu <>2015-02-05 11:00:09 (GMT)
committerChromeOS Commit Bot <>2015-02-05 21:03:13 (GMT)
commit538b9b0d393953ba54217d9ab23a2f09803a9646 (patch)
parent59fc8005a6391146c3df65684df15c8aed4775ce (diff)
depthcharge: spi-nand: Remove "wait until ready" in the write pathstabilize-6771.Bfactory-auron-6772.B
The "wait until ready" call reads the STATUS (0xC0) register, and waits until the OIP (Operation-In-Progress) flag is cleared. Currently, it is used after page program and block erase commands are sent, to check they are completed and the device is idle. The call is also used between the cache programand the page program commands. However, the GD5F specification does not mention it as part of the write sequence. Instead, the write sequence is specified as: 1) Program Load (cache program) 2) Write Enable 3) Program Execute (page program) 4) Read Status register and wait until ready Intensive testing shows it's actually problematic, causing pages to not get properly written. Remove it. BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; works as expected; BRANCH=none Author: Ezequiel Garcia <> Change-Id: I6dc5a34222f486f17fc0f94b84748a2f25d17346 Signed-off-by: Ionela Voinescu <> Reviewed-on: Reviewed-by: Daniel Ehrenberg <>
1 files changed, 0 insertions, 4 deletions
diff --git a/src/drivers/storage/mtd/nand/spi_nand.c b/src/drivers/storage/mtd/nand/spi_nand.c
index 7b7b9fa..d82d4d9 100644
--- a/src/drivers/storage/mtd/nand/spi_nand.c
+++ b/src/drivers/storage/mtd/nand/spi_nand.c
@@ -403,10 +403,6 @@ static int spi_nand_write_page(MtdDev *mtd, int pageno, unsigned int length,
return ret;
- ret = spi_nand_wait_till_ready(dev);
- if (ret < 0)
- return ret;
ret = spi_nand_write_enable(dev);
if (ret < 0) {
printf("spi_nand: write enable on page program failed\n");