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authorShawn Nematbakhsh <shawnn@chromium.org>2015-04-03 00:04:27 (GMT)
committerChromeOS Commit Bot <chromeos-commit-bot@chromium.org>2015-04-04 04:02:20 (GMT)
commite2a93abfa30a41d412880e71d8968baa91a99117 (patch)
tree67ff8861b9653ffd1d0b8037eaad24a29c5b080e
parent8e94b15b05c5eb02e5eea783b399912c6b0b7a93 (diff)
downloaddepthcharge-release-R43-6946.B.tar.gz
depthcharge-release-R43-6946.B.tar.xz
cros_ec: Add MEC LPC protocol variantstabilize-6946.55.Brelease-R43-6946.B
MEC accesses certain I/O regions through its EMI interface rather than through LPC directly. BUG=chrome-os-partner:38224 TEST=Manual on Glower. Verify system boots kernel cleanly in recovery mode. BRANCH=None Change-Id: I405917999efb1d5760266acd4819e5f30f8167f7 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/263814 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
-rw-r--r--src/drivers/ec/cros/lpc.c58
-rw-r--r--src/drivers/ec/cros/lpc.h2
-rw-r--r--src/drivers/ec/cros/lpc_mec.h56
3 files changed, 116 insertions, 0 deletions
diff --git a/src/drivers/ec/cros/lpc.c b/src/drivers/ec/cros/lpc.c
index 93efcdb..6ce8090 100644
--- a/src/drivers/ec/cros/lpc.c
+++ b/src/drivers/ec/cros/lpc.c
@@ -25,6 +25,7 @@
#include "base/container_of.h"
#include "drivers/ec/cros/lpc.h"
+#include "drivers/ec/cros/lpc_mec.h"
/* Timeout waiting for a flash erase command to complete */
static const int CROS_EC_CMD_TIMEOUT_MS = 5000;
@@ -57,6 +58,59 @@ static void lpc_read(uint8_t *data, uint16_t port, int size)
*data++ = inb(port++);
}
+static void mec_emi_write_address(uint16_t addr, uint8_t access_mode)
+{
+ /* Address relative to start of EMI range */
+ addr -= MEC_EMI_RANGE_START;
+ outb((addr & 0xfc) | access_mode, MEC_EMI_EC_ADDRESS_B0);
+ outb((addr >> 8) & 0x7f, MEC_EMI_EC_ADDRESS_B1);
+}
+
+static void mec_io_bytes(int write, uint8_t *data, uint16_t port, int size) {
+ int i = 0;
+ int io_addr;
+
+ if (size == 0)
+ return;
+
+ /* Initialize I/O at desired address */
+ mec_emi_write_address(port, ACCESS_TYPE_LONG_AUTO_INCREMENT);
+
+ /* Skip bytes in case of misaligned port */
+ io_addr = MEC_EMI_EC_DATA_B0 + (port & 0x3);
+ while (i < size) {
+ while (io_addr <= MEC_EMI_EC_DATA_B3) {
+ if (write)
+ outb(data[i++], io_addr++);
+ else
+ data[i++] = inb(io_addr++);
+
+ /* Extra bounds check in case of misaligned length */
+ if (i == size)
+ return;
+ }
+
+ /* Access [B0, B3] on each loop pass */
+ io_addr = MEC_EMI_EC_DATA_B0;
+ }
+}
+
+static void mec_write(const uint8_t *data, uint16_t port, int size)
+{
+ if (port >= MEC_EMI_RANGE_START && port <= MEC_EMI_RANGE_END)
+ mec_io_bytes(1, (uint8_t *)data, port, size);
+ else
+ lpc_write(data, port, size);
+}
+
+static void mec_read(uint8_t *data, uint16_t port, int size)
+{
+ if (port >= MEC_EMI_RANGE_START && port <= MEC_EMI_RANGE_END)
+ mec_io_bytes(0, data, port, size);
+ else
+ lpc_read(data, port, size);
+}
+
static int send_command(CrosEcBusOps *me, uint8_t cmd, int cmd_version,
const void *dout, uint32_t dout_len,
void *din, uint32_t din_len)
@@ -236,6 +290,10 @@ CrosEcLpcBus *new_cros_ec_lpc_bus(CrosEcLpcBusVariant variant)
bus->ops.read = lpc_read;
bus->ops.write = lpc_write;
break;
+ case CROS_EC_LPC_BUS_MEC:
+ bus->ops.read = mec_read;
+ bus->ops.write = mec_write;
+ break;
default:
printf("%s: Unknown LPC variant %d\n", __func__, variant);
free(bus);
diff --git a/src/drivers/ec/cros/lpc.h b/src/drivers/ec/cros/lpc.h
index daafc49..4351a99 100644
--- a/src/drivers/ec/cros/lpc.h
+++ b/src/drivers/ec/cros/lpc.h
@@ -36,6 +36,8 @@ typedef enum
{
/* LPC access to command / data / memmap buffers */
CROS_EC_LPC_BUS_GENERIC,
+ /* Access memmap range through EMI unit */
+ CROS_EC_LPC_BUS_MEC,
} CrosEcLpcBusVariant;
CrosEcLpcBus *new_cros_ec_lpc_bus(CrosEcLpcBusVariant variant);
diff --git a/src/drivers/ec/cros/lpc_mec.h b/src/drivers/ec/cros/lpc_mec.h
new file mode 100644
index 0000000..26be0d2
--- /dev/null
+++ b/src/drivers/ec/cros/lpc_mec.h
@@ -0,0 +1,56 @@
+/*
+ * Chromium OS EC driver - LPC MEC interface
+ *
+ * Copyright 2015 Google Inc.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __DRIVERS_EC_CROS_LPC_MEC_H__
+#define __DRIVERS_EC_CROS_LPC_MEC_H__
+
+/* For MEC, access ranges 0x800 thru 0x9ff using EMI interface instead of LPC */
+#define MEC_EMI_RANGE_START EC_HOST_CMD_REGION0
+#define MEC_EMI_RANGE_END (EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SIZE)
+
+enum {
+ /* 8-bit access */
+ ACCESS_TYPE_BYTE = 0x0,
+ /* 16-bit access */
+ ACCESS_TYPE_WORD = 0x1,
+ /* 32-bit access */
+ ACCESS_TYPE_LONG = 0x2,
+ /*
+ * 32-bit access, read or write of MEC_EMI_EC_DATA_B3 causes the
+ * EC data register to be incremented.
+ */
+ ACCESS_TYPE_LONG_AUTO_INCREMENT = 0x3,
+};
+
+/* EMI registers are relative to base */
+#define MEC_EMI_BASE 0x800
+#define MEC_EMI_HOST_TO_EC (MEC_EMI_BASE + 0)
+#define MEC_EMI_EC_TO_HOST (MEC_EMI_BASE + 1)
+#define MEC_EMI_EC_ADDRESS_B0 (MEC_EMI_BASE + 2)
+#define MEC_EMI_EC_ADDRESS_B1 (MEC_EMI_BASE + 3)
+#define MEC_EMI_EC_DATA_B0 (MEC_EMI_BASE + 4)
+#define MEC_EMI_EC_DATA_B1 (MEC_EMI_BASE + 5)
+#define MEC_EMI_EC_DATA_B2 (MEC_EMI_BASE + 6)
+#define MEC_EMI_EC_DATA_B3 (MEC_EMI_BASE + 7)
+
+#endif /* __DRIVERS_EC_CROS_LPC_H__ */