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2017-07-24rockchip: rk3288: Add support for drive-strength in PINCTRLHEADmasterRomain Perier1-1/+9
Currently, drive-strenght to 12ma are described and supposed to be used on RK3288. However, the pinctrl driver for this SoC only handles muxing and pull up/pull down via PU/PD control registers. So complex IPs like GMAC are working in normal ethernet 100mbps, but not at 1gbps typically. This commit adds support for handling drive-strength of 12ma, when it's defined in the DT. Signed-off-by: Romain Perier <romain.perier@collabora.com>
2017-07-17rockchip: rk3288: Revert MAC_TXCLK in pinctrl for GMACgmac_rockchip_fixesRomain Perier1-0/+4
This reverts TXCLK toggling that was accidently dropped while reworking commit 2454b719fb87 ("rockchip: rk3288: Add pinctrl support for the gmac ethernet interface"). So the TX clock is enabled and we can use GMAC_ROCKCHIP in 1Gbps when basic PINCTRL support is enabled (!PINTRL_FULL). Fixes: 2454b719fb87 ("rockchip: rk3288: Add pinctrl support for the...") Signed-off-by: Romain Perier <romain.perier@collabora.com>
2017-07-17rockchip: rk3288: Remove phy reset GPIO pull upRomain Perier1-3/+1
We should not handle this pin explicitly from pinctrl. GMAC driver takes care of it by using a "reset-gpio" in the DT. This commit removes pull up for GPIO4B0. Fixes: 2454b719fb87 ("rockchip: rk3288: Add pinctrl support for the...") Signed-off-by: Romain Perier <romain.perier@collabora.com>
2017-07-13ARM: dts: rockchip: WIP for sdmmc on RK3188Romain Perier2-2/+4
Signed-off-by: Romain Perier <romain.perier@collabora.com>
2017-07-13mmc: rockchip: WIP sdmmc for RK3188Romain Perier3-2/+16
Signed-off-by: Romain Perier <romain.perier@collabora.com>
2017-07-13hacks to make Radxa Rock work with usb ethernet and usb storageHeiko Stuebner3-2/+61
Signed-off-by: Romain Perier <romain.perier@collabora.com>
2017-07-12rockchip: clk: rk3399: remove unused fields from priv-structuresPhilipp Tomsich1-2/+0
This removes the unused 'rate' field from both rk3399_pmuclk_priv and rk3399_clk_priv. I didn't bother to check where this came from (i.e. what the historical context of these was), but only verified that these are indeed unused across all code-paths. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-12rockchip: clk: rk3368: remove unused fields from rk3368_clk_privPhilipp Tomsich1-2/+0
The rk3368_clk_priv has two unused fields: rate, has_bwadj. This removes them as there's no need for either (i.e. has_bwadj is always true for the RK3368, according to its TRM). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-12rockchip: clk: rk3368: use correct (i.e. 'rk3368_clk_priv') structure for ↵Philipp Tomsich1-1/+1
auto-alloc The clk driver for the RK3368 picked the wrong data structure's size for its auto-alloc size: the size was calculated on the structure representing the CRU hardware block instead of the priv structure. As the CRU's register file is much larger than the driver's priv, this did not cause any pain (except wasting memory). Fix this by using the correct data structure's size. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-12rockchip: spl: make boot0 hook TPL safePhilipp Tomsich1-1/+12
When building for a TPL/SPL setup (e.g. on the RK3368), we need the TPL stage to have the extra space for for the 'Rockchip SPL name' (i.e. 'RK33' word). Yet, the SPL will start execution at its first word (i.e. the first word in the SPL binary needs to be a valid instruction). To make things a bit more involved, CONFIG_SPL_BUILD is defined both for the SPL and the TPL stage. To avoid having to explicitly test for the first stage (TPL, if and only if TPL and SPL are built, SPL otherwise), this commit modifies the sequence to repeat the 'b reset' (instead of reserving 4 bytes of undefined space) at the start of the boot0 hook: if overwritten (and execution starts at the second word), the first instruction is still a 'b reset'... if not overwritten, we start on a 'b reset' as well. This solution wouldn't even require the check whether we are in the SPL/TPL build (i.e. CONFIG_SPL_BUILD), but we leave this check in for documentation purposes. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-11rockchip: rk3288: Add pinctrl support for the gmac ethernet interfaceSjoerd Simons2-0/+296
Add support for the gmac ethernet interface to pinctrl. This hardcodes the setup to match that of the firefly and Radxa Rock2 boards, using the RGMII phy mode for gmac interface and GPIO4B0 as the phy reset GPIO. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Romain Perier <romain.perier@collabora.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11rockchip: evb-rk3328: enable boot on regulatorKever Yang1-1/+8
Enable all the boot-on regulator in default. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11rockchip: dts: rk3328-evb: add sdmmc-pwren regulatorKever Yang1-0/+8
Use fixed regulator for sdmmc-pwren for sdmmc power. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11rockchip: pinctrl: rk3328: use gpio instead of sdmmc-pwrenKever Yang1-4/+2
SDMMC-PWREN is a pin to control voltage for SDMMC IO, it may be high active or low active, the dwmmc driver always assume the sdmmc-pwren as high active. Kernel treat this pin as fixed regulator instead of a pin from controller, and then it can set in dts file upon board schematic, that's a good solution, we can also do this in u-boot. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11doc: rockchip: Add phyCORE-RK3288 RDK to board listWadim Egorov1-1/+2
Signed-off-by: Wadim Egorov <w.egorov@phytec.de> Acked-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11rockchip: Add basic support for phyCORE-RK3288 SoM based carrier boardWadim Egorov11-0/+981
The phyCORE-RK3288 is a SoM (System on Module) containing a RK3288 SoC. The module can be connected to different carrier boards. It can be also equipped with different RAM, SPI flash and eMMC variants. The Rapid Development Kit option is using the following setup: - 1 GB DDR3 RAM (2 Banks) - 1x 4 KB EEPROM - DP83867 Gigabit Ethernet PHY - 16 MB SPI Flash - 4 GB eMMC Flash Add basic support for the PCM-947 carrier board, a RK3288 based development board made by PHYTEC. This board works in a combination with the phyCORE-RK3288 System on Module. Signed-off-by: Wadim Egorov <w.egorov@phytec.de> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11power: regulator: rk8xx: Allow input current/charger shutdown configurationWadim Egorov2-0/+36
The RK818 PMIC contains a charger. Add very basic charger functionality to be able to regulate the USB input current and charger shutdown limits. Signed-off-by: Wadim Egorov <w.egorov@phytec.de> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11power: regulator: rk8xx: Build get_ldo_reg only for SPLWadim Egorov1-19/+21
Enabling CONFIG_SPL_POWER_SUPPORT will cause a compiler warning: ‘get_ldo_reg’ defined but not used [-Wunused-function] Let's wrap get_ldo_reg(), rk808_ldo and rk818_ldo with ENABLE_DRIVER which is only set for non SPL builds. Signed-off-by: Wadim Egorov <w.egorov@phytec.de> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11rockchip: dts: rk3399: control vbus of typec by fixed regulatorMeng Dongyang1-2/+14
Add fixed regulator for the port of typec0 and typec1 to control vbus instead of gpio. Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11rockchip: dts: rk3328: support and enable dwc2Meng Dongyang2-0/+24
Enable dwc2 controller and add fixed regulator for dwc2 controller to control vbus. Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11rockchip: rk3328: board: add support of dwc2 gadgetMeng Dongyang1-0/+42
Probe dwc2 udc in the function of board_usb_start to enable usb gadget function. Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11usb: dwc2: use dev_read_bool() instead of fdt_getprop()Meng Dongyang1-10/+6
Use dev_read_bool() instead of fdt_getprop() to get the property from DTS. And add a comment for "hnp-srp-disable" property to fully describe its effect. Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11rockchip: dts: rk3328: add fixed regulator node for xhciMeng Dongyang1-2/+18
The driver changes gpio to fixed regulator to control vbus, so add fixed regulator node in DTS for xhci driver. Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11usb: Kconfig: migrate USB_DWC2 to KconfigPhilipp Tomsich29-10/+30
This change migrates the USB_DWC2 configuration item to Kconfig and runs moveconfig to adjust header files and defconfig. Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com> Split off into a separate patch: Ran moveconfig to migrate other boards: Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11rockchip: dts: rk3328: add fixed regulator node for xhciMeng Dongyang1-1/+10
The driver changes gpio to fixed regulator to control vbus, so add fixed regulator node in DTS for xhci driver. Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11usb: host: xhci-rockchip: use fixed regulator to control vbusMeng Dongyang1-18/+18
Use fixed regulator to control the voltage of vbus. Enable vbus supply when usb start and disable vbus supply when usb stop. Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11usb: Kconfig: config USB_XHCI_ROCKCHIP depends on DM_REGULATOR and DM_USBMeng Dongyang1-0/+2
The xhci-rockchip driver depends on DM_REGULATOR and DM_USB. So add dependent features for xhci-rockchip driver in Kconfig. Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11rockchip: rk3036: sync os_reg2 define with other socKever Yang1-2/+3
Rockchip using the same bit definition for dram info and write to os_reg, the col and bw info is not correct and let's fix it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11rockchip: rk3036 remove CONFIG_RAM from defconfigKever Yang2-2/+0
rk3036 sdram driver does not use DM, remove CONFIG_RAM first. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11rockchip: video: mipi: Modify format type for debug messageeric.gao@rock-chips.com1-4/+4
Modify format type for debug message. Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
2017-07-11rockchip: video: mipi: Modify variable type for arm32 compatibilityeric.gao@rock-chips.com1-7/+7
Some address relevant varibable is defined originally as u64. To compatible with arm32, this patch change them to uintptr_t type. Signed-off-by: Eric Gao <eric.gao@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-11rockchip: pwm: fix the register layout for the PWM controllereric.gao@rock-chips.com1-1/+1
According to rk3288 spec, the pwm register order is: PWM_PWM0_CNT, PWM_PWM0_PERIOD_HPR, PWM_PWM0_DUTY_LPR, PWM_PWM0_CTRL but the source code's order is: struct rk3288_pwm { u32 cnt; u32 duty_lpr; u32 period_hpr; u32 ctrl; }; So, correct it here. It is the same as RK3399. Signed-off-by: Eric Gao <eric.gao@rock-chips.com> Edited the commit message: Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11Revert "mmc: dw_mmc: rockchip: select proper card clock"Kever Yang1-2/+2
The origin patch get rockchip dwmmc by name 'ciu', which lead to the SPL not able to remove 'clock-names' node in dts. I'm not saying this is not correct, but I would prefer to handle this in dts or clock driver to save memory for SPL. For example the rk3288 SPL size has out of memory if not enable BACK_TO_BROM option, there are many other SoCs has less internal memory than rk3288. This reverts commit 480a9b834c661fc88217f50bdf780192c3018d66. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11rockchip: firefly-rk3399: enable dwmmc driver for the boardKever Yang1-1/+1
Enable mmc_dw_rockchip driver, disable CONFIG_SPL_OF_PLATDATA first for some dependence patches still not merged. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Vagrant Cascadian <vagrant@debian.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-11rockchip: firefly-rk3399: dts: enable sdmmc deviceKever Yang1-0/+7
Enable sdmmc device and add the spl boot device sequence. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11rockchip: dwmmc: use max-frequency when OF_PLATDATA enabledKever Yang1-1/+2
Since the 'clock-freq-min-max' is deprecated, we use max-frequency for all rockchip SoC dwmmc controller. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11rockchip: rk3328: dtsi use max-frequency for mmc nodeKever Yang1-4/+4
Since the 'clock-freq-min-max' is deprecated, we use max-frequency. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11rockchip: rk3288: dtsi use max-frequency for mmc nodeKever Yang1-4/+4
Since the 'clock-freq-min-max' is deprecated, we use max-frequency. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11rockchip: rk3036: dtsi use max-frequency for mmc nodeKever Yang1-1/+1
Since the 'clock-freq-min-max' is deprecated, we use max-frequency. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11rockchip: add evb_rk3229 boardKever Yang7-0/+145
evb_rk3229 is a RK3229 based board, with: - 8GB eMMC; - 1GB DDR SDRAM; - 2 USB2.0 HOST port; - 1 MAC port; - 1 HDMI port; - IR; - WiFi; Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11rockchip: rk322x: add sysreset driverKever Yang1-0/+45
Rockchip rk322x sysreset is much like rk3036 and other Rockchip SoCs, only difference is that the target register address is different. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11rockchip: rk322x: add basic soc supportKever Yang10-0/+404
Enable soc support for SPL and U-boot skeleton. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11rockchip: rk322x: add dts fileKever Yang3-0/+1025
The dts files are from kernel and with modify to adapt U-Boot. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11rockchip: rk322x: add pinctrl driverKever Yang4-0/+824
Add init pinctrl driver support for: - i2c; - spi; - uart; - pwm; - emmc/sdmmc; Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11rockchip: rk322x: add clock driverKever Yang3-0/+629
Add clock driver init support for: - cpu, bus clock init; - emmc, sdmmc clock; - ddr clock; Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Fixed format specified (%x -> %p) in clk_rk322x.c: Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11rockchip: mkimage: add support for rk322x socKever Yang1-0/+1
Add support for rk322x package header in mkimage tool. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11rockchip: rv1108: disable CONFIG_RAM before we have driverKever Yang1-1/+0
The rv1108 do not have DRAM driver now, so disable it first, or else it will get conflict with the sdram common code. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11rockchip: correct the bank0 ram sizeKever Yang9-52/+39
The bank0 ram size should be the DRAM size minus reserved size, the DRAM size may be 1GB, 2GB, 4GB, we can not hard code it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Added DECLARE_GLOBAL_DATA_PTR for RK3328, RK3368 and RK3399: Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11rockchip: dts: rk3368: add dmc nodeKever Yang1-0/+7
Add dmc node to enable sdram driver. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11rockchip: dts: rk3328: add dmc nodeKever Yang1-0/+7
Add a dmc node for sdram driver. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>