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authorKever Yang <kever.yang@rock-chips.com>2017-06-13 08:10:46 (GMT)
committerPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>2017-07-11 10:13:48 (GMT)
commit64a524b08ae7fe2a88355c3d671bf3764e968ecb (patch)
tree820662ea2f5aaa2312cff832cb6268636f4063c1
parentd59b9dd39787fe4c2753d2e4942a53ff5eb986ff (diff)
downloadu-boot-rockchip-64a524b08ae7fe2a88355c3d671bf3764e968ecb.tar.gz
u-boot-rockchip-64a524b08ae7fe2a88355c3d671bf3764e968ecb.tar.xz
rockchip: rk3036: sync os_reg2 define with other soc
Rockchip using the same bit definition for dram info and write to os_reg, the col and bw info is not correct and let's fix it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
-rw-r--r--arch/arm/mach-rockchip/rk3036/sdram_rk3036.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
index ec8305c..460dd60 100644
--- a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
+++ b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
@@ -710,11 +710,12 @@ static void sdram_all_config(struct rk3036_sdram_priv *priv)
os_reg = config.ddr_type << DDR_TYPE_SHIFT |
0 << DDR_CHN_CNT_SHIFT |
(config.rank - 1) << DDR_RANK_CNT_SHIFT |
- (config.col - 1) << DDR_COL_SHIFT |
+ (config.col - 9) << DDR_COL_SHIFT |
(config.bank == 3 ? 0 : 1) << DDR_BANK_SHIFT |
(config.cs0_row - 13) << DDR_CS0_ROW_SHIFT |
cs1_row << DDR_CS1_ROW_SHIFT |
- 1 << DDR_BW_SHIFT | config.bw << DDR_DIE_BW_SHIFT;
+ 1 << DDR_BW_SHIFT |
+ (2 >> config.bw) << DDR_DIE_BW_SHIFT;
writel(os_reg, &priv->grf->os_reg[1]);
}